Jim Ballingall| Eetimes

A new approach to computer R&D is being born from the rise of mobile systems and the slowing of CMOS scaling.

In 2012, several of the world’s leading computer scientists and engineers collaborated on a whitepaper that describes a strategy for computing R&D. The whitepaper sets forth several goals to be achieved by the end of this decade across the spectrum of computing scale from tiny sensors to expansive datacenters.

The goal is to improve the energy efficiency of computers by two to three orders of magnitude. Furthermore we want to realize by the end of this decade an exa-op datacenter that consumes no more than 10 megawatts.

The whitepaper describes a path forward to pursue these goals. The thesis is that cross-layer work in circuits, architecture, and software are essential to make substantial gains and avoid as much as 50 percent dark silicon, effectively unused transistors in a technology node. There will be no shortage of transistors — 50 billion or so available for an 8nm SoC processor. The question is will the advances in architecture and software be sufficient to leverage this enormous sea of transistors effectively, and drive energy efficiency forward by three orders of magnitude.

A rising class of mobile systems demands this kind of support. Mobility is reshaping all facets of the industry, driving new development in servers and the cloud. By 2011, smartphones were out-shipping PCs, and tablets were clearly diminishing the revenues of the Wintel notebook PC franchise.

The Industry-Academia Partnership (IAP) is bringing together industry and university partners to meet the technology needs of the future datacenter and cloud. This work spans the solutions for compute, storage, and networking and the full suite of software needed to support the cloud and its emerging use cases and applications.

The IAP hosts workshops open to students on university campuses with presentations by experts from academia and industry. We invite interested parties to join us in this pursuit, and plan to report on progress and innovations on these pages on a regular basis.

This work will help shore up in computing a weakening foundation of CMOS technology that is compromising the performance and cost of future mobile devices, desktop computers and servers. A recent study by researchers at Stanford estimates that roughly half of the gains in computational performance since 1985 were realized by advances in computer architecture and software, with the other half by advances in semiconductor manufacturing technology.

On the architectural side, multicore processors have been the key innovation in the past decade, arising as a response to the so-called “power wall.” Frequencies were dialed back to reduce dynamic power, and work was distributed to multiple smaller cores with shorter pipelines.

But like semiconductor process technology, multicore is not expected to offer large gains in the future, at least not on its own. One analysis projects that speedups of only four- to eight-fold will be achieved over the next 10 years, as multicore rides the technology migration of CMOS to 8nm. That’s one reason why we need some new thinking now.


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